名称:出租车计费器设计VHDL代码Quartus DE2-115开发板
软件:Quartus
语言:VHDL
代码功能:
2km内起步价,起步价7元,超出2km后每公里1元,数码管显示里程和费用,按键控制开始和停止
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
本代码已在DE2-115开发板验证,DE2-115开发板如下,其他开发板可以修改管脚适配:
演示视频:
设计文档:
1.工程文件
2.程序文件
3.管脚分配
4.程序编译
5.RTL图
6.仿真图
计费模块仿真图
显示模块仿真图
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --出租车计价器 ENTITY taxi_fee IS PORT ( clk : IN STD_LOGIC;--时钟 reset_n : IN STD_LOGIC;--复位 stop : IN STD_LOGIC;--停车 start : IN STD_LOGIC;--开车 HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);--数码管0 HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);--数码管1 HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);--数码管2 HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)--数码管3 ); END taxi_fee; ARCHITECTURE behave OF taxi_fee IS --计费控制模块 COMPONENT taxi_state IS PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; stop : IN STD_LOGIC; start : IN STD_LOGIC; mileage_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); totel_money_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; --数码管显示模块 COMPONENT HEX IS PORT ( clk : IN STD_LOGIC; SMG_1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); SMG_2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; SIGNAL mileage_out : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL totel_money_out : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN --调用计费控制模块 i_taxi_state : taxi_state PORT MAP ( clk => clk, reset_n => reset_n, stop => stop, start => start, mileage_out => mileage_out, totel_money_out => totel_money_out ); --调用数码管显示模块 i_HEX : HEX PORT MAP ( clk => clk, smg_1 => mileage_out, smg_2 => totel_money_out, hex0 => HEX0, hex1 => HEX1, hex2 => HEX2, hex3 => HEX3 ); END behave;
点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1208
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