名称:方波、三角波、正弦波发生器设计VHDL代码Quartus仿真
软件:Quartus
语言:VHDL
代码功能:
方波、三角波、正弦波发生器VHDL
1、使用VHDL设计波形发生器
2、可以控制输出输出正弦、方波、三角波
3、通过频率控制字控制输出波形频率
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
演示视频:
设计文档:
DDS原理
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
5. Testbench
6. 仿真图
整体仿真图
相位累加器模块
波形选择模块
正弦波ROM
三角波ROM
方波ROM
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY DDS_top IS PORT ( clk_50M : IN STD_LOGIC; wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);--01输出sin,10输出方波,11输出三角波 frequency : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--频率控制字,控制输出波形频率,值越大,频率越大 wave : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--输出波形 ); END DDS_top; ARCHITECTURE behave OF DDS_top IS --例化模块 COMPONENT wave_sel IS PORT ( clk_50M : IN STD_LOGIC; wave_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0); douta_fangbo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta_sanjiao : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta_sin : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wave : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT Frequency_ctrl IS PORT ( clk_50M : IN STD_LOGIC; frequency : IN STD_LOGIC_VECTOR(7 DOWNTO 0); addra : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT sin_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; COMPONENT fangbo_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; COMPONENT sanjiao_ROM IS PORT ( address: IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; SIGNAL addra : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL douta_fangbo : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL douta_sanjiao : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL douta_sin : STD_LOGIC_VECTOR(7 DOWNTO 0);
点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1263
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