名称:Quartus简易乐曲发生器VHDL代码AX301开发板
软件:Quartus
语言:VHDL
代码功能:
12、简易乐曲发生器
利用音名与频率的关系制作简易乐曲发生器,要求能循环播放一首乐曲,并显示乐曲演奏时对应的音符。
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
本代码已在AX301开发板验证,开发板如下,其他开发板可以修改管脚适配:
演示视频:
设计文档:
1. 工程文件
2. 程序文件
3. 程序编译
4. 管脚分配
5. RTL图
6. Testbench
7. 仿真图
整体仿真图
频率控制字产生模块
音乐控制模块
显示模块
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --音乐播放器 ENTITY music IS PORT ( sysclk : IN STD_LOGIC;--50M晶振 stop_key : IN STD_LOGIC;--reset start_key : IN STD_LOGIC;--开始 led : OUT STD_LOGIC;--指示灯 spkout : OUT STD_LOGIC;--蜂鸣器输出 bit_select : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);--数码管位选 seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管段选 ); END music; ARCHITECTURE trans OF music IS COMPONENT music_ctrl IS PORT ( sysclk : IN STD_LOGIC; stop_key : IN STD_LOGIC; start_key : IN STD_LOGIC; tonecode : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); tonestep : IN STD_LOGIC_VECTOR(9 DOWNTO 0); led : OUT STD_LOGIC; spkout : OUT STD_LOGIC ); END COMPONENT; COMPONENT display IS PORT ( clk : IN STD_LOGIC; tonecode : IN STD_LOGIC_VECTOR(7 DOWNTO 0); bit_select : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); seg_select : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT musicdec IS PORT ( tonecode : IN STD_LOGIC_VECTOR(7 DOWNTO 0); tonestep : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; SIGNAL tonestep : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL tonecode : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL music_num : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL clk_valid : STD_LOGIC; SIGNAL led_buf : STD_LOGIC; BEGIN clk_valid <= sysclk; --频率控制字产生模块 u_musicdec : musicdec PORT MAP ( tonecode => tonecode,--输入简谱 tonestep => tonestep--输出频率控制字 ); --音乐控制模块 i_music_ctrl : music_ctrl PORT MAP ( sysclk => sysclk, start_key => start_key, stop_key => stop_key, tonecode => tonecode,--简谱 tonestep => tonestep,--频率控制字 spkout => spkout, led => led ); --显示模块 i_display : display PORT MAP ( clk => sysclk, tonecode => tonecode, bit_select => bit_select,--数码管位选 seg_select => seg_select--数码管段选 ); END trans;
点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=340
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