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Cambridge, UK 8 June, 2022. Agile Analog™, the analog IP innovators, has signed its first licensee in China. “We opened our APAC regional sales and engineering office in January this year,” said Barry Paterson, Agile Analog’s CEO. “We thought that there would be a big demand for our unique analog IP solutions in the Asia-Pacific region and so we are delighted to have signed our first license for the region in just a couple of months. Key to the deal is us having local support for the customer to provide immediate answers to any engineering questions.”
英国剑桥，2022年6月8日。模拟IP创新者Agile Analog™ 在中国签署了第一份授权协议。 “我们于今年1月开设了亚太地区销售和工程办事处，”Agile Analog首席执行官Barry Paterson说。“我们认为亚太地区对我们独特的模拟IP解决方案的需求会很大，因此我们很高兴在短短几个月内签署了该地区的第一个授权协议。达成交易的关键是我们为客户提供本地支持，以便立即回答任何工程问题。
The customer will be using a set of Agile Analog IP in its new SSD Controller chip. This includes Bandgap Voltage Reference, Power On Reset, Digital Temperature Sensor and IR-Drop Detector. “Having these in a ready-to-use, drop-in form that exactly meets the required specifications enabled the customer to shorten the time to market compared to alternative solutions, which have to be custom made,” added Lisa Yang, who heads up the APAC operations. “Our ability to shortening product development times makes a huge difference in today’s competitive market, particularly in China where the competition with rivals is fierce. BOM costs is another area where we help customers as we can bring analog functions, which are normally handled by discrete components, onto the ASIC to save costs.”
客户将在其新的SSD控制器芯片中使用一组Agile Analog IP。这包括带隙基准电压源、上电复位、数字温度传感器和 IR 压降检测器。“与必须定制的替代解决方案相比，以完全符合所需规格的即用型直接插入形式提供这些产品，使客户能够缩短上市时间，”负责亚太地区运营的Lisa Yang补充道。“我们缩短产品开发时间的能力在当今竞争激烈的市场中产生了巨大的影响，特别是在与竞争对手竞争激烈的中国。BOM成本是我们帮助客户的另一个领域，因为我们可以将通常由分立元件处理的模拟功能引入ASIC以节省成本。
Traditionally, analog IP blocks have to be manually redesigned for each application and process technology but Agile Analog has a unique way to automatically generate analog IP to exactly meet the customer’s specifications and process technology. Called Composa™, it uses tried and tested analog IP circuits that are in the company’s Composa library. Effectively, the design-once-and-re-use-many-times model of digital IP now applies to analog IP for the first time. As the analog IP circuits in the Composa library have been extensively tested and used in previous designs, and are fully validated every time they are generated, this gives a similar level of reassurance to the digital IP world’s ‘silicon-proven’.
传统上，模拟IP模块必须针对每种应用和工艺技术进行手动重新设计，但Agile Analog 具有自动生成模拟IP的独特方式，以完全满足客户的规格和工艺技术。它被称为Composa™ 其使用Composa库中经过试验和测试的模拟IP电路。实际上，数字IP的“一次设计，多次重用”模式现在首次应用于模拟IP。由于Composa库中的模拟IP电路已在以前的设计中进行了广泛的测试和使用，并且每次生成时都经过全面验证，因此这为数字IP世界的“硅验证”提供了类似的保证。
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