一、vcs
vcs -full64-R-l sim.log-debug_access+all-timescale=1ns/1ps-sverilog+define+A=1+libext+.v-y ../model-v ../lib/stdcell.v-f rtl.listtb.sv
二、nc/irun/xrun
xrun -64bit-l sim.log-access rwc-timescale 1ns/1ps-sv-define A=1-libext .v-y ../model-v ../lib/stdcell.v-f rtl.listtb.sv
三、verdi
verdi-timescale=1ns/1ps-sverilog+define+A=1+libext+.v-y ../model-v ../lib/stdcell.v-f rtl.listtb.sv
如果要同时加载波形,再加一行:
-ssf xxx.fsdb
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